February 8, 2012--Innovative Integration introduces PEX6-COP FPGA computing core, a flexible FPGA coprocessor card that integrates a Virtex-6 FPGA computing core with an industry-standard FMC IO module on a half-length PCI Express desktop or server card. The FPGA computing core features the Xilinx Virtex-6 FPGA family, in densities up to LX550 and SX475. The SX475 provides over 2000 DSP MAC elements operating at up to 500 MHz. The FPGA core has two 18MB QDRII+ SRAM banks, two 1024MB LPDDR2 DRAM banks, and a 128MB DDR3 bank. Each memory is directly connected to the FPGA and is fully independent.
For system communications, the PEX6-COP has a PCI Express and a secondary x4 port. The PCIe port is a x8, Gen2 interface capable of up to 3 GB/s sustained operation with 4 GB/s burst rate. The secondary port can be used as Aurora ports (x4 to x1), as a second PCI Express x4 port, or using a custom protocol. An FMC site, conforming to VITA 57, provides configurable IO for the PEX6-COP. The FMC site has full support for the high pin count connector, with over 80 LVDS pairs directly connected to the FPGA and x10 lanes at up to 5 Gbps per lane.
FMC also is readily adapted to application-specific custom modules. The PEX-COP family power is less than 15W for typical operation. The card is available rated for wide-temperature (-40 to 85C) and 100% humidity with conformal coating. The FPGA logic can be fully customized using the Frame Work Logic tool set. The toolset provides support for both MATLAB and RTL designs.
The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP cores for a range of signal processing cores for applications such as wireless, RADAR and SIGINT such as DDC, demodulation, and FFT are also available. Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features are provided.
