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Matrox introduces Supersight e2 imaging platform

Source: Matrox Graphics Inc.
09 June, 2009
Supersight e2 offers OEMs performance and flexibility for machine vision applications that generate extraordinary amounts of data.

June 9, 2009 – Matrox Imaging launched its high-performance computing (HPC) platform for industrial imaging: Matrox Supersight e2.Matrox Supersight e2 offers OEMs unprecedented performance and flexibility for machine vision applications that generate extraordinary amounts of data. Applications such as semiconductor wafer and mask inspection, flat panel display (FPD) inspection, and CT scanning benefit from performance gains with Matrox Supersight e2 by leveraging multiple clusters of CPUs, GPUs and FPGAs. Matrox Supersight e2 provides an environment for considerable data and task-level parallel processing through the interconnection of CPUs, GPUs and FPGAs using a unique PCI Express (PCIe) x16 2.0 (Gen2) switched fabric that removes I/O bottlenecks between the multiple processors.

Imaging applications differ significantly from traditional IT datacenter or HPC applications where the application is typically compute-bound. With imaging applications, the gigapixels per second of data leave most platforms I/O-bound. Matrox Supersight e2 offers a solution to this unique architectural challenge as traditional Blade servers and 1U “pizza boxes” simply do not have the I/O bandwidth to distribute images to the processors and accelerators. Matrox Supersight e2 ensures that the performance gains from accelerators or additional processors are not lost during simple data transfers, as seen in Blade or 1U “pizza box” environments.

Furthermore, the switched fabric lets developers “re-cluster” the compute elements to maintain optimal performance as the application is tuned or evolves with time. Applications for Matrox Supersight e2 are developed with the Matrox Imaging Library (MIL) and its Distributed MIL API. As MIL is supported on all Matrox Imaging hardware platforms, development on Matrox Supersight e2 is simplified and ensures the source code is portable across all devices, from nodes with 32 CPU cores and 4 FPGAs, to a node with 8 CPU cores, 1 FPGA and 6 GPUs and everything in between.

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